Value Members

1.  final def !=(arg0: Any): Boolean

   Definition Classes

   AnyRef → Any

2.  final def ##: Int

   Definition Classes

   AnyRef → Any

3.  final def ==(arg0: Any): Boolean

   Definition Classes

   AnyRef → Any

4.  lazy val TestDirectory: File

   Parent directory for tests

5.  final def asInstanceOf[T0]: T0

   Definition Classes

   Any

6.  def clone(): AnyRef

   Attributes

   protected[lang]

   Definition Classes

   AnyRef

   Annotations

   @throws(classOf[java.lang.CloneNotSupportedException]) @native()

7.  def copyResourceToFile(name: String, file: File): Unit

   Copy the contents of a resource to a destination file.

   Copy the contents of a resource to a destination file.

   name

   the name of the resource

   file

   the file to write it into

8.  def cppToExe(prefix: String, dir: File): ProcessBuilder
9.  def createTestDirectory(testName: String): File

   Create a test directory

   Create a test directory

   Will create outer directory called testName then inner directory based on the current time

10.  final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

11.  def equals(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef → Any

12.  def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String = ""): Boolean
13.  def executeExpectingSuccess(prefix: String, dir: File): Boolean
14.  def finalize(): Unit

    Attributes

    protected[lang]

    Definition Classes

    AnyRef

    Annotations

    @throws(classOf[java.lang.Throwable])

15.  def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder

    compule chirrtl to verilog by using a separate process

    compule chirrtl to verilog by using a separate process

    prefix

    basename of the file

    dir

    directory where file lives

    returns

    true if compiler completed successfully

16.  final def getClass(): Class[_ <: AnyRef]

    Definition Classes

    AnyRef → Any

    Annotations

    @native()

17.  def getLogger: Logger

    Definition Classes

    LazyLogging

18.  def hashCode(): Int

    Definition Classes

    AnyRef → Any

    Annotations

    @native()

19.  final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

20.  val logger: Logger

    Attributes

    protected

    Definition Classes

    LazyLogging

21.  def loggingProcessLogger: ProcessLogger
22.  def makeHarness(template: (String) => String, post: String)(f: File): File
23.  final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

24.  final def notify(): Unit

    Definition Classes

    AnyRef

    Annotations

    @native()

25.  final def notifyAll(): Unit

    Definition Classes

    AnyRef

    Annotations

    @native()

26.  final def synchronized[T0](arg0: => T0): T0

    Definition Classes

    AnyRef

27.  def timeStamp: String
28.  def toString(): String

    Definition Classes

    AnyRef → Any

29.  def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean = false, resourceFileName: String = firrtl.transforms.BlackBoxSourceHelper.defaultFileListName, extraCmdLineArgs: Seq[String] = Seq.empty): ProcessBuilder

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.

    Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.

    If the file BlackBoxSourceHelper.fileListName (or an overridden .f resource filename that is specified with the optional resourceFileName parameter) exists in the output directory, it contains a list of source files to be included. Filter out any files in the vSources sequence that are in this file so we don't include the same file multiple times. This complication is an attempt to work-around the fact that clients used to have to explicitly include additional Verilog sources. Now, more of that is automatic.

    dutFile

    name of the DUT .v without the .v extension

    dir

    output directory

    vSources

    list of additional Verilog sources to compile

    cppHarness

    C++ testharness to compile/link against

    suppressVcd

    specifies if VCD tracing should be suppressed

    resourceFileName

    specifies what filename to look for to find a .f file

    extraCmdLineArgs

    list of additional command line arguments

30.  final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws(classOf[java.lang.InterruptedException])

31.  final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws(classOf[java.lang.InterruptedException])

32.  final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws(classOf[java.lang.InterruptedException]) @native()