Value Members

1.  final def !=(arg0: Any): Boolean

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2.  final def ##: Int

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3.  final def ==(arg0: Any): Boolean

   Definition Classes

   AnyRef → Any

4.  def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   readPortClocks

   A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

   writePortClocks

   A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

   readwritePortClocks

   A sequence of clocks for each read-write port; and the above two conditions must hold

   readLatency

   The number of cycles >= 1 between a read request and read response (applies to all ports)

   writeLatency

   The number of cycles >= 1 between a write request and read response (applies to all ports)

   memoryFile

   A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

5.  def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   readPortClocks

   A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

   writePortClocks

   A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

   readwritePortClocks

   A sequence of clocks for each read-write port; and the above two conditions must hold

   memoryFile

   A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

6.  def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   readPortClocks

   A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

   writePortClocks

   A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

   readwritePortClocks

   A sequence of clocks for each read-write port; and the above two conditions must hold

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

7.  def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   numReadPorts

   The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

   numWritePorts

   The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

   numReadwritePorts

   The number of desired read/write ports >= 0, and the above two conditions must hold

   memoryFile

   A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

8.  def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   numReadPorts

   The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

   numWritePorts

   The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

   numReadwritePorts

   The number of desired read/write ports >= 0, and the above two conditions must hold

   readLatency

   The number of cycles >= 1 between a read request and read response (applies to all ports)

   writeLatency

   The number of cycles >= 1 between a write request and read response (applies to all ports)

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

9.  def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

   The data type of the memory element

   size

   The desired size of the inner SyncReadMem

   numReadPorts

   The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

   numWritePorts

   The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

   numReadwritePorts

   The number of desired read/write ports >= 0, and the above two conditions must hold

   returns

   A new SRAMInterface wire containing the control signals for each instantiated port

   Exceptions thrown

   java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

   Note

   This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

10.  final def asInstanceOf[T0]: T0

    Definition Classes

    Any

11.  def clone(): AnyRef

    Attributes

    protected[lang]

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    @throws(classOf[java.lang.CloneNotSupportedException]) @native()

12.  final def eq(arg0: AnyRef): Boolean

    Definition Classes

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13.  def equals(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef → Any

14.  def finalize(): Unit

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    protected[lang]

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    @throws(classOf[java.lang.Throwable])

15.  final def getClass(): Class[_ <: AnyRef]

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    @native()

16.  def hashCode(): Int

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    @native()

17.  final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

18.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    readPortClocks

    A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

    A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

    A sequence of clocks for each read-write port; and the above two conditions must hold

    readLatency

    The number of cycles >= 1 between a read request and read response (applies to all ports)

    writeLatency

    The number of cycles >= 1 between a write request and read response (applies to all ports)

    memoryFile

    A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

    ,

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

19.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    readPortClocks

    A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

    A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

    A sequence of clocks for each read-write port; and the above two conditions must hold

    memoryFile

    A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

    ,

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

20.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    readPortClocks

    A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

    A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

    A sequence of clocks for each read-write port; and the above two conditions must hold

    readLatency

    The number of cycles >= 1 between a read request and read response (applies to all ports)

    writeLatency

    The number of cycles >= 1 between a write request and read response (applies to all ports)

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

    ,

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

21.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    readPortClocks

    A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

    A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

    A sequence of clocks for each read-write port; and the above two conditions must hold

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

    ,

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

22.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    numReadPorts

    The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

    The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

    The number of desired read/write ports >= 0, and the above two conditions must hold

    readLatency

    The number of cycles >= 1 between a read request and read response (applies to all ports)

    writeLatency

    The number of cycles >= 1 between a write request and read response (applies to all ports)

    memoryFile

    A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

23.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    numReadPorts

    The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

    The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

    The number of desired read/write ports >= 0, and the above two conditions must hold

    memoryFile

    A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

24.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    numReadPorts

    The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

    The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

    The number of desired read/write ports >= 0, and the above two conditions must hold

    readLatency

    The number of cycles >= 1 between a read request and read response (applies to all ports)

    writeLatency

    The number of cycles >= 1 between a write request and read response (applies to all ports)

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

25.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

    The data type of the memory element

    size

    The desired size of the inner SyncReadMem

    numReadPorts

    The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

    The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

    The number of desired read/write ports >= 0, and the above two conditions must hold

    returns

    A new SRAMInterface wire containing the control signals for each instantiated port

    Exceptions thrown

    java.lang.IllegalArgumentException if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

    Note

    This does *not* return the SyncReadMem itself, you must interact with it using the returned bundle

26.  final def ne(arg0: AnyRef): Boolean

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27.  final def notify(): Unit

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28.  final def notifyAll(): Unit

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29.  final def synchronized[T0](arg0: => T0): T0

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30.  def toString(): String

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31.  final def wait(): Unit

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32.  final def wait(arg0: Long, arg1: Int): Unit

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33.  final def wait(arg0: Long): Unit

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