object SRAM
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- SRAM.scala
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- implicit class SRAMDescriptionInstanceMethods extends AnyRef
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- def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- readPortClocks
A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0
- writePortClocks
A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0
- readwritePortClocks
A sequence of clocks for each read-write port; and the above two conditions must hold
- memoryFile
A memory file whose path is emitted as Verilog directives to initialize the inner
SyncReadMem- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- readPortClocks
A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0
- writePortClocks
A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0
- readwritePortClocks
A sequence of clocks for each read-write port; and the above two conditions must hold
- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- numReadPorts
The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0
- numWritePorts
The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0
- numReadwritePorts
The number of desired read/write ports >= 0, and the above two conditions must hold
- memoryFile
A memory file whose path is emitted as Verilog directives to initialize the inner
SyncReadMem- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- numReadPorts
The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0
- numWritePorts
The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0
- numReadwritePorts
The number of desired read/write ports >= 0, and the above two conditions must hold
- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
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- def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit
Clock, rather than being given the implicit clock.- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- readPortClocks
A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0
- writePortClocks
A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0
- readwritePortClocks
A sequence of clocks for each read-write port; and the above two conditions must hold
- memoryFile
A memory file whose path is emitted as Verilog directives to initialize the inner
SyncReadMem- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
The size of each
,Clocksequence determines the corresponding number of read, write, and read-write portsThis does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit
Clock, rather than being given the implicit clock.- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- readPortClocks
A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0
- writePortClocks
A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0
- readwritePortClocks
A sequence of clocks for each read-write port; and the above two conditions must hold
- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
The size of each
,Clocksequence determines the corresponding number of read, write, and read-write portsThis does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- numReadPorts
The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0
- numWritePorts
The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0
- numReadwritePorts
The number of desired read/write ports >= 0, and the above two conditions must hold
- memoryFile
A memory file whose path is emitted as Verilog directives to initialize the inner
SyncReadMem- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
- def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.
Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).
- T
The data type of the memory element
- size
The desired size of the inner
SyncReadMem- numReadPorts
The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0
- numWritePorts
The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0
- numReadwritePorts
The number of desired read/write ports >= 0, and the above two conditions must hold
- returns
A new
SRAMInterfacewire containing the control signals for each instantiated port
- Note
This does *not* return the
,SyncReadMemitself, you must interact with it using the returned bundleRead-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.