object Trace
The util that records the reference map from original Data/Module annotated in Chisel and final FIRRTL.
- Source
- Trace.scala
class Dut extends Module { val a = WireDefault(Bool()) Trace.traceName(a) } val annos = (new ChiselStage).execute(Seq(ChiselGeneratorAnnotation(() => new Dut))) val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[CollideModule] // get final reference of `a` Seq(ReferenceTarget("Dut", "Dut", Seq.empty, "a", Seq.empty)) val firrtlReferenceOfDutA = finalTarget(annos)(dut.a)
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- def finalTarget(annos: AnnotationSeq)(x: HasId): Seq[CompleteTarget]
Get
CompleteTargetof the targetxforannos.Get
CompleteTargetof the targetxforannos. This API can be used to find the final reference to a signal or module which is marked bytraceName - def finalTargetMap(annos: AnnotationSeq): Map[CompleteTarget, Seq[CompleteTarget]]
Get all traced signal/module for
annosThis API can be used to gather all final reference to the signal or module which is marked bytraceName - def finalize(): Unit
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- def traceName(x: Data): Unit
Trace a Data name.
Trace a Data name. This does NOT add "don't touch" semantics to the traced data. If you want this behavior, use an explicit chisel3.dontTouch.
- def traceName(x: RawModule): Unit
Trace a Instance name.
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.