Chisel/FIRRTL
Chisel3
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General Cookbook
Naming Cookbook
Troubleshooting
Explanations
Motivation
Supported Hardware
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Bundles and Vecs
Combinational Circuits
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Width Inference
Functional Abstraction
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Sequential Circuits
Memories
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Blackboxes
Enumerations
Functional Module Creation
Muxes and Input Selection
Multiple Clock Domains
Reset
Polymorphism and Parameterization
Printing in Chisel
Naming
Unconnected Wires
Annotations
Appendix
Chisel3 vs. Chisel2
Experimental Features
Upgrading From Scala 2.11
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sbt Subproject
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Developer Documentation
Tips and tricks for Chisel developers:
Embedding Chisel as an sbt subproject
Test Coverage