Class

chisel3.core

BlackBox

Related Doc: package core

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abstract class BlackBox extends BaseBlackBox

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

Example:
  1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

    IBUFDS #(.DIFF_TERM("TRUE"),
             .IOSTANDARD("DEFAULT")) ibufds (
     .IB(ibufds_IB),
     .I(ibufds_I),
     .O(ibufds_O)
    );

    To instantiate it, a BlackBox can be used like following:

    import chisel3._
    import chisel3.experimental._
    // Example with Xilinx differential buffer IBUFDS
    class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                      "IOSTANDARD" -> "DEFAULT"
                         )) {
      val io = IO(new Bundle {
        val O = Output(Clock()) // IO names will be the same
        val I = Input(Clock())  // (without 'io_' in prefix)
        val IB = Input(Clock()) //
      })
    }
Note

The parameters API is experimental and may change

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  1. BlackBox
  2. BaseBlackBox
  3. BaseModule
  4. HasId
  5. InstanceId
  6. AnyRef
  7. Any
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Visibility
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Instance Constructors

  1. new BlackBox(params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions)

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Abstract Value Members

  1. abstract def io: Record

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Concrete Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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    Definition Classes
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  4. def IO[T <: Data](iodef: T): T

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    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit

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    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit

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    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean

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    Attributes
    protected
  9. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any
  10. def circuitName: String

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    Attributes
    protected
    Definition Classes
    HasId
  11. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  12. def desiredName: String

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    Desired name of this module.

    Desired name of this module. Override this to give this module a custom, perhaps parametric, name.

    Definition Classes
    BaseModule
  13. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  14. def equals(that: Any): Boolean

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    Definition Classes
    HasId → AnyRef → Any
  15. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  16. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any
  17. def getIds: Seq[HasId]

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    Attributes
    protected
    Definition Classes
    BaseModule
  18. def getModulePorts: Seq[Data]

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    Attributes
    protected
    Definition Classes
    BaseModule
  19. def hashCode(): Int

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    Definition Classes
    HasId → AnyRef → Any
  20. def instanceName: String

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    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  21. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any
  22. final lazy val name: String

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    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  23. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

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    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    BaseModule
  24. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  25. final def notify(): Unit

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    Definition Classes
    AnyRef
  26. final def notifyAll(): Unit

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    Definition Classes
    AnyRef
  27. val params: Map[String, Param]

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  28. def parentModName: String

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    Definition Classes
    HasId → InstanceId
  29. def parentPathName: String

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    Definition Classes
    HasId → InstanceId
  30. def pathName: String

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    Definition Classes
    HasId → InstanceId
  31. def portsContains(elem: Data): Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule
  32. def portsSize: Int

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    Attributes
    protected
    Definition Classes
    BaseModule
  33. def suggestName(name: ⇒ String): BlackBox.this.type

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    Definition Classes
    HasId
  34. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef
  35. final def toNamed: ModuleName

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    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  36. def toString(): String

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    Definition Classes
    AnyRef → Any
  37. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  38. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
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    Annotations
    @throws( ... )
  39. final def wait(arg0: Long): Unit

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    Definition Classes
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    Annotations
    @throws( ... )

Deprecated Value Members

  1. def annotate(annotation: ChiselAnnotation): Unit

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    Attributes
    protected
    Definition Classes
    BaseModule
    Annotations
    @deprecated
    Deprecated

    (Since version 3.1) Use chisel3.experimental.annotate instead

Inherited from BaseBlackBox

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

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