Packages

c

chisel3

MultiIOModule

abstract class MultiIOModule extends RawModule

Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.

Source
RawModule.scala
Note

Module instantiations must be wrapped in a Module() call.

Linear Supertypes
RawModule, BaseModule, HasId, internal.InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. MultiIOModule
  2. RawModule
  3. BaseModule
  4. HasId
  5. InstanceId
  6. AnyRef
  7. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new MultiIOModule()(implicit moduleCompileOptions: CompileOptions)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit

    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  10. val clock: Clock
  11. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  12. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  13. def desiredName: String

    Desired name of this module.

    Desired name of this module. Override this to give this module a custom, perhaps parametric, name.

    Definition Classes
    BaseModule
  14. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  15. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  16. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  17. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  18. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  19. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  20. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  21. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  22. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  23. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  24. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  25. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  26. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    BaseModule
  27. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  28. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  29. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  30. def parentModName: String
    Definition Classes
    HasId → InstanceId
  31. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  32. def pathName: String
    Definition Classes
    HasId → InstanceId
  33. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  34. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  35. val reset: Reset
  36. def suggestName(name: ⇒ String): MultiIOModule.this.type
    Definition Classes
    HasId
  37. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  38. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  39. def toString(): String
    Definition Classes
    AnyRef → Any
  40. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  41. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  42. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  43. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()

Deprecated Value Members

  1. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModule → InstanceId
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) toNamed API is deprecated -- use toTarget instead

    Note

    Should not be called until circuit elaboration is complete

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped