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chisel3

Driver

object Driver extends BackendCompilationUtilities

Annotations
@deprecated
Deprecated

(Since version 3.2.4) Please switch to chisel3.stage.ChiselStage. Driver will be removed in 3.4.

Source
Driver.scala
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  1. Driver
  2. BackendCompilationUtilities
  3. BackendCompilationUtilities
  4. LazyLogging
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Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. lazy val TestDirectory: File
    Definition Classes
    BackendCompilationUtilities
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. val chiselVersionString: String
  7. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  8. def compileFirrtlToVerilog(prefix: String, dir: File): Boolean

    Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

    Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

    prefix

    basename of the file

    dir

    directory where file lives

    returns

    true if compiler completed successfully

    Definition Classes
    BackendCompilationUtilities
  9. def copyResourceToFile(name: String, file: File): Unit
    Definition Classes
    BackendCompilationUtilities
  10. def cppToExe(prefix: String, dir: File): ProcessBuilder
    Definition Classes
    BackendCompilationUtilities
  11. def createTestDirectory(testName: String): File
    Definition Classes
    BackendCompilationUtilities
  12. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  13. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  14. def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String): Boolean
    Definition Classes
    BackendCompilationUtilities
  15. def executeExpectingSuccess(prefix: String, dir: File): Boolean
    Definition Classes
    BackendCompilationUtilities
  16. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  17. def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder
    Definition Classes
    BackendCompilationUtilities
  18. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  19. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  20. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  21. val logger: Logger
    Attributes
    protected
    Definition Classes
    LazyLogging
  22. def loggingProcessLogger: ProcessLogger
    Definition Classes
    BackendCompilationUtilities
  23. def makeHarness(template: (String) ⇒ String, post: String)(f: File): File
    Definition Classes
    BackendCompilationUtilities
  24. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  25. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  26. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  27. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  28. def timeStamp: String
    Definition Classes
    BackendCompilationUtilities
  29. def toString(): String
    Definition Classes
    AnyRef → Any
  30. def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean, resourceFileName: String): ProcessBuilder
    Definition Classes
    BackendCompilationUtilities
  31. val version: String
  32. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  33. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  34. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  35. def yosysExpectFailure(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)]): Boolean
    Definition Classes
    BackendCompilationUtilities
  36. def yosysExpectSuccess(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)]): Boolean
    Definition Classes
    BackendCompilationUtilities

Deprecated Value Members

  1. def dumpAnnotations(ir: Circuit, optName: Option[File]): File

    Emit the annotations of a circuit

    Emit the annotations of a circuit

    ir

    The circuit containing annotations to be emitted

    optName

    An optional filename (will use s"${ir.name}.json" otherwise)

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.4) Migrate to chisel3.stage.ChiselStage. This will be removed in 3.4.

  2. def dumpFirrtl(ir: Circuit, optName: Option[File]): File

    Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.

    Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.

    If no File is given as input, it will dump to a default filename based on the name of the top Module.

    optName

    File to dump to. If unspecified, defaults to "<topmodule>.fir".

    returns

    The File the circuit was dumped to.

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.4) Migrate to chisel3.stage.ChiselStage. This will be removed in 3.4.

  3. def dumpProto(c: Circuit, optFile: Option[File]): File

    Dump the elaborated Circuit to ProtoBuf.

    Dump the elaborated Circuit to ProtoBuf.

    If no File is given as input, it will dump to a default filename based on the name of the top Module.

    c

    Elaborated Chisel Circuit.

    optFile

    Optional File to dump to. If unspecified, defaults to "<topmodule>.pb".

    returns

    The File the circuit was dumped to.

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.4) Migrate to chisel3.stage.ChiselStage. This will be removed in 3.4.

  4. def elaborate[T <: RawModule](gen: () ⇒ T): Circuit

    Elaborate the Module specified in the gen function into a Chisel IR Circuit.

    Elaborate the Module specified in the gen function into a Chisel IR Circuit.

    gen

    A function that creates a Module hierarchy.

    returns

    The resulting Chisel IR in the form of a Circuit. (TODO: Should be FIRRTL IR)

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.4) Use ChiselStage.elaborate or use a ChiselStage class. This will be removed in 3.4.

  5. def emit[T <: RawModule](ir: Circuit): String

    Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.

    Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.

    ir

    Chisel IR Circuit, generated e.g. by elaborate().

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use (new chisel3.stage.ChiselStage).emitChirrtl

  6. def emit[T <: RawModule](gen: () ⇒ T): String

    Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.

    Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.

    gen

    A function that creates a Module hierarchy.

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use (new chisel3.stage.ChiselStage).emitChirrtl. This will be removed in 3.4.

  7. def emitVerilog[T <: RawModule](gen: ⇒ T): String

    Elaborate the Module specified in the gen function into Verilog.

    Elaborate the Module specified in the gen function into Verilog.

    gen

    A function that creates a Module hierarchy.

    returns

    A String containing the design in Verilog.

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use (new chisel3.stage.ChiselStage).emitVerilog. This will be removed in 3.4.

  8. def execute(args: Array[String], dut: () ⇒ RawModule): ChiselExecutionResult

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    args

    The options specified, command line style

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use chisel3.stage.ChiselStage.execute. This will be removed in 3.4.

  9. def execute(optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, dut: () ⇒ RawModule): ChiselExecutionResult

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    optionsManager

    The options specified

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use chisel3.stage.ChiselStage.execute. This will be removed in 3.4.

  10. def main(args: Array[String]): Unit

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    args

    unused args

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use chisel3.stage.ChiselMain. This will be removed in 3.4.

  11. def parseArgs(args: Array[String]): Unit
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) Use chisel3.stage.ChiselStage with '--target-directory'. This will be removed in 3.4.

  12. def targetDir(): String
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.2) This has no effect on Chisel3 Driver! This will be removed in 3.4.

  13. def toFirrtl(ir: Circuit): Circuit

    Convert the given Chisel IR Circuit to a FIRRTL Circuit.

    Convert the given Chisel IR Circuit to a FIRRTL Circuit.

    ir

    Chisel IR Circuit, generated e.g. by elaborate().

    Annotations
    @deprecated
    Deprecated

    (Since version 3.2.4) Use ChiselStage.convert or use a ChiselStage class. This will be removed in 3.4.

Inherited from LazyLogging

Inherited from AnyRef

Inherited from Any

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