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firrtl.stage

OptimizeForFPGA

object OptimizeForFPGA extends HasShellOptions

This flag enables a set of options that guide the FIRRTL compilation flow to ultimately generate Verilog that is more amenable to using for synthesized FPGA designs. Currently, this flag affects only memories, as the need to emit memories that support downstream inference of hardened RAM macros. These options are not intended to be specialized to any particular vendor; instead, they aim to emit simple Verilog that more closely reflects traditional human-written definitions of synchronous-read memories.

1) Enable the firrtl.passes.memlib.InferReadWrite transform to reduce port count, where applicable.

2) Use the firrtl.transforms.SimplifyMems transform to Lower aggregate-typed memories with always-high masks to packed memories without splitting them into multiple independent ground-typed memories.

3) Use the firrtl.passes.memlib.SeparateWriteClocks transform to ensure that each write port of a multiple-write, synchronous-read memory with 'undefined' collision behavior ultimately maps to a separate clocked process in the emitted Verilog. This avoids the issue of implicitly constraining cross-port collision and write ordering behavior and helps simplify inference of true dual-port RAM macros.

4) Use the firrtl.passes.memlib.SetDefaultReadUnderWrite to specify that memories with undefined read-under-write behavior should map to emitted microarchitectures characteristic of "read-first" ports by default. This eliminates the difficulty of inferring a RAM macro that matches the strict semantics of "write-first" ports.

5) Add a firrtl.passes.memlib.PassthroughSimpleSyncReadMemsAnnotation to allow some synchronous-read memories and readwrite ports to pass through firrtl.passes.memlib.VerilogMemDelays without introducing explicit pipeline registers or splitting ports.

6) Add a firrtl.annotations.MemorySynthInit to enable memory initialization values to be synthesized.

Source
FirrtlCompilerTargets.scala
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  4. final def addOptions(p: OptionParser[AnnotationSeq]): Unit

    Add all shell (command line) options to an option parser

    Add all shell (command line) options to an option parser

    p

    an option parser

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  16. val options: Seq[ShellOption[Unit]]

    A sequence of options provided

    A sequence of options provided

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  17. final def synchronized[T0](arg0: ⇒ T0): T0
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