object MemDelayAndReadwriteTransformer

Source
VerilogMemDelays.scala
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Type Members

  1. case class SplitStatements(decls: Seq[Statement], conns: Seq[Connect]) extends Product with Serializable
  2. case class WithValid(valid: Expression, payload: Seq[Expression]) extends Product with Serializable

Value Members

  1. final def !=(arg0: Any): Boolean
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  2. final def ##(): Int
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  3. final def ==(arg0: Any): Boolean
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  4. def AND(e1: Expression, e2: Expression): DoPrim
  5. def NOT(e: Expression): DoPrim
  6. def allPortKinds(expr: Expression): Boolean

    Determines if all RefLikeExpression in this Expression are of kind PortKind

  7. final def asInstanceOf[T0]: T0
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  8. def clone(): AnyRef
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    protected[lang]
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    @throws( ... ) @native()
  9. def condConnect(l: WithValid, r: WithValid): Seq[Connect]
  10. def condConnect(c: Expression)(l: Expression, r: Expression): Connect
  11. def connect(l: WithValid, r: WithValid): Seq[Connect]
  12. def connect(l: Expression, r: Expression): Connect
  13. final def eq(arg0: AnyRef): Boolean
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  14. def equals(arg0: Any): Boolean
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  15. def finalize(): Unit
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    protected[lang]
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    @throws( classOf[java.lang.Throwable] )
  16. final def getClass(): Class[_]
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    @native()
  17. def hashCode(): Int
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    @native()
  18. final def isInstanceOf[T0]: Boolean
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  19. final def ne(arg0: AnyRef): Boolean
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  20. final def notify(): Unit
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    @native()
  21. final def notifyAll(): Unit
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    @native()
  22. def pipelineWithValid(ns: Namespace)(clock: Expression, depth: Int, src: WithValid, nameTemplate: Option[WithValid] = None): (WithValid, Seq[Statement], Seq[Connect])
  23. final def synchronized[T0](arg0: ⇒ T0): T0
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  24. def toString(): String
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  25. final def wait(): Unit
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    @throws( ... )
  26. final def wait(arg0: Long, arg1: Int): Unit
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    @throws( ... )
  27. final def wait(arg0: Long): Unit
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    @throws( ... ) @native()

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