Packages

class VerilogEmitter extends SeqTransform with Emitter

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Inherited
  1. VerilogEmitter
  2. Emitter
  3. SeqTransform
  4. SeqTransformBased
  5. Transform
  6. DependencyAPI
  7. TransformLike
  8. LazyLogging
  9. AnyRef
  10. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new VerilogEmitter()

Type Members

  1. class VerilogRender extends AnyRef

    Used by getRenderer, it has machinery to produce verilog from IR.

    Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def AND(e1: WrappedExpression, e2: WrappedExpression): Expression
  5. def addFormalStatement(formals: Map[Expression, ArrayBuffer[Seq[Any]]], clk: Expression, en: Expression, stmt: Seq[Any], info: Info, msg: StringLit): Unit
  6. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  7. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  8. def emit(state: CircuitState, writer: Writer): Unit
    Definition Classes
    VerilogEmitterEmitter
  9. def emit(x: Any, top: Int)(implicit w: Writer): Unit
  10. def emit(x: Any)(implicit w: Writer): Unit
  11. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  12. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  13. def execute(state: CircuitState): CircuitState

    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes
    VerilogEmitterSeqTransformTransform
  14. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  15. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  16. def getLogger: Logger
    Definition Classes
    LazyLogging
  17. def getRenderer(descriptions: Seq[DescriptionAnnotation], m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer): VerilogRender

    Gets a reference to a verilog renderer.

    Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.

    descriptions

    comments to be emitted

    m

    the start module

    moduleMap

    a way of finding other modules

    writer

    where rendering will be placed

    returns

    the render reference

  18. def getRenderer(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer): VerilogRender

    Gets a reference to a verilog renderer.

    Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.

    m

    the start module

    moduleMap

    a way of finding other modules

    writer

    where rendering will be placed

    returns

    the render reference

  19. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  20. def inputForm: LowForm.type

    The firrtl.CircuitForm that this transform requires to operate on

    The firrtl.CircuitForm that this transform requires to operate on

    Definition Classes
    VerilogEmitterTransform
  21. def invalidates(a: Transform): Boolean

    A function that, given *another* transform (parameter a) will return true if this transform invalidates/undos the effects of the *other* transform (parameter a).

    A function that, given *another* transform (parameter a) will return true if this transform invalidates/undos the effects of the *other* transform (parameter a).

    a

    transform

    Definition Classes
    EmitterTransformDependencyAPI
  22. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  23. val logger: Logger
    Attributes
    protected
    Definition Classes
    LazyLogging
  24. def name: String

    A convenience function useful for debugging and error messages

    A convenience function useful for debugging and error messages

    Definition Classes
    TransformTransformLike
  25. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  26. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  27. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  28. def op_stream(doprim: DoPrim): Seq[Any]
  29. def optionalPrerequisiteOf: Seq[Nothing]

    A sequence of transforms to add this transform as an optionalPrerequisite.

    A sequence of transforms to add this transform as an optionalPrerequisite. The use of optionalPrerequisiteOf enables the transform declaring them to always run before some other transforms. However, declaring optionalPrerequisiteOf will not result in the sequence of transforms executing.

    This is useful for providing an ordering constraint to guarantee that other transforms (e.g., emitters) will not be scheduled before you.

    Definition Classes
    VerilogEmitterTransformDependencyAPI
    Note

    This method **will not** result in the listed transforms running. If you want to add multiple transforms at once, you should use a DependencyManager with multiple targets.

  30. def optionalPrerequisites: Seq[Dependency[Transform]]

    All transforms that, if a prerequisite of *another* transform, will run before this transform.

    All transforms that, if a prerequisite of *another* transform, will run before this transform.

    Definition Classes
    TransformDependencyAPI
    Note

    The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.

  31. def outputForm: LowForm.type

    The firrtl.CircuitForm that this transform outputs

    The firrtl.CircuitForm that this transform outputs

    Definition Classes
    VerilogEmitterTransform
  32. val outputSuffix: String

    An output suffix to use if the output of this Emitter was written to a file

    An output suffix to use if the output of this Emitter was written to a file

    Definition Classes
    VerilogEmitterEmitter
  33. def prerequisites: Seq[Dependency[Transform]]

    All transform that must run before this transform

    All transform that must run before this transform

    Definition Classes
    VerilogEmitterTransformDependencyAPI
    Note

    The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.

  34. def remove_root(ex: Expression): Expression
  35. final def runTransform(state: CircuitState): CircuitState

    Perform the transform and update annotations.

    Perform the transform and update annotations.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes
    Transform
  36. def runTransforms(state: CircuitState): CircuitState
    Attributes
    protected
    Definition Classes
    SeqTransformBased
  37. def stringify(tpe: GroundType): String
  38. def stringify(param: Param): String

    Turn Params into Verilog Strings

  39. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  40. val tab: String
  41. def toString(): String
    Definition Classes
    AnyRef → Any
  42. def transform(state: CircuitState): CircuitState

    A mathematical transform on some type

    A mathematical transform on some type

    returns

    an output object of the same type

    Definition Classes
    TransformTransformLike
  43. def transforms: Seq[Transform]

    Preamble for every emitted Verilog file

    Preamble for every emitted Verilog file

    Definition Classes
    VerilogEmitterSeqTransformBased
  44. def v_print(e: Expression, colNum: Int)(implicit w: Writer): Int
  45. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  46. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  47. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  48. def wref(n: String, t: Type): WRef

Deprecated Value Members

  1. def dependents: Seq[Dependency[Transform]]

    All transforms that must run after this transform

    All transforms that must run after this transform

    This is a means of prerequisite injection into some other transform. Normally a transform will define its own prerequisites. Dependents exist for two main situations:

    First, they improve the composition of optional transforms. If some first transform is optional (e.g., an expensive validation check), you would like to be able to conditionally cause it to run. If it is listed as a prerequisite on some other, second transform then it must always run before that second transform. There's no way to turn it off. However, by listing the second transform as a dependent of the first transform, the first transform will only run (and be treated as a prerequisite of the second transform) if included in a list of target transforms that should be run.

    Second, an external library would like to inject some first transform before a second transform inside FIRRTL. In this situation, the second transform cannot have any knowledge of external libraries. The use of a dependent here allows for prerequisite injection into FIRRTL proper.

    Definition Classes
    DependencyAPI
    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.

    Note

    The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.

    See also

    firrtl.passes.CheckTypes for an example of an optional checking firrtl.Transform

Inherited from Emitter

Inherited from SeqTransform

Inherited from SeqTransformBased

Inherited from Transform

Inherited from DependencyAPI[Transform]

Inherited from TransformLike[CircuitState]

Inherited from LazyLogging

Inherited from AnyRef

Inherited from Any

Ungrouped