Package

firrtl

passes

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package passes

Visibility
  1. Public
  2. All

Type Members

  1. case class DataRef(exp: Expression, male: String, female: String, mask: String, rdwrite: Boolean) extends Product with Serializable

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  2. class Errors extends AnyRef

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  3. class InlineInstances extends Transform

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  4. case class MPort(name: String, clk: Expression) extends Product with Serializable

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  5. case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) extends Product with Serializable

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  6. trait Pass extends Transform

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    Pass is simple transform that is generally part of a larger Transform Has an UnknownForm, because larger Transform should specify form

  7. class PassException extends Exception

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  8. class PassExceptions extends Exception

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Value Members

  1. object CInferMDir extends Transform with Pass

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  2. object CInferTypes extends Transform with Pass

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  3. object CheckChirrtl extends Transform with Pass

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  4. object CheckGenders extends Transform with Pass

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  5. object CheckHighForm extends Transform with Pass

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  6. object CheckInitialization extends Transform with Pass

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    Reports errors for any references that are not fully initialized

    Reports errors for any references that are not fully initialized

    Note

    Assumes single connection (ie. no last connect semantics)

    ,

    This pass looks for firrtl.WVoids left behind by ExpandWhens

  7. object CheckTypes extends Transform with Pass

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  8. object CheckWidths extends Transform with Pass

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  9. object CommonSubexpressionElimination extends Transform with Pass

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  10. object ConvertFixedToSInt extends Transform with Pass

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    Replaces FixedType with SIntType, and correctly aligns all binary points

  11. object DeadCodeElimination extends Transform

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  12. object ExpandConnects extends Transform with Pass

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  13. object ExpandWhens extends Transform with Pass

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    Expand Whens

    Expand Whens

    This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches

    Note

    Assumes all references are declared

    ,

    Assumes bulk connects and isInvalids have been expanded

  14. object InferTypes extends Transform with Pass

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  15. object InferWidths extends Transform with Pass

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  16. object InlineAnnotation

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  17. object Legalize extends Transform with Pass

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  18. object LowerTypes extends Transform

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    Removes all aggregate types from a firrtl.ir.Circuit

    Removes all aggregate types from a firrtl.ir.Circuit

    Example:
    1. wire foo : { a : UInt<32>, b : UInt<16> }

      lowers to

      wire foo_a : UInt<32>
      wire foo_b : UInt<16>
    Note

    Assumes firrtl.ir.Connects and firrtl.ir.IsInvalids only operate on firrtl.ir.Expressions of ground type

    ,

    Assumes firrtl.ir.SubAccesses have been removed

  19. object MemPortUtils

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  20. object PadWidths extends Transform with Pass

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  21. object PullMuxes extends Transform with Pass

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  22. object RemoveAccesses extends Transform with Pass

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    Removes all firrtl.WSubAccess from circuit

  23. object RemoveCHIRRTL extends Transform

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  24. object RemoveEmpty extends Transform with Pass

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  25. object RemoveValidIf extends Transform with Pass

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    Remove ValidIf and replace IsInvalid with a connection to zero

  26. object ReplaceAccesses extends Transform with Pass

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    Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop

  27. object ResolveGenders extends Transform with Pass

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  28. object ResolveKinds extends Transform with Pass

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  29. object SplitExpressions extends Transform with Pass

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  30. object ToWorkingIR extends Transform with Pass

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  31. object Uniquify extends Transform

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    Resolve name collisions that would occur in LowerTypes

    Resolve name collisions that would occur in LowerTypes

    Example:
    1. wire a = { b, c }[2]
      wire a_0

      This lowers to:

      wire a__0_b
      wire a__0_c
      wire a__1_b
      wire a__1_c
      wire a_0

      There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a

    Note

    Must be run after InferTypes because ir.DefNodes need type

  32. object VerilogModulusCleanup extends Transform with Pass

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    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))

    This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes

  33. object VerilogPrep extends Transform with Pass

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    Makes changes to the Firrtl AST to make Verilog emission easier

    Makes changes to the Firrtl AST to make Verilog emission easier

    - For each instance, adds wires to connect to each port

    • Note that no Namespace is required because Uniquify ensures that there will be no collisions with the lowered names of instance ports - Also removes Attaches where a single Port OR Wire connects to 1 or more instance ports
    • These are expressed in the portCons of WDefInstConnectors
    Note

    The result of this pass is NOT legal Firrtl

  34. object VerilogRename extends Transform with Pass

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  35. object VerilogWrap extends Transform with Pass

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  36. object ZeroWidth extends Transform

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  37. package clocklist

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  38. object createMask

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  39. package memlib

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  40. object toBitMask

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    Given a mask, return a bitmask corresponding to the desired datatype.

    Given a mask, return a bitmask corresponding to the desired datatype. Requirements:

    • The mask type and datatype must be equivalent, except any ground type in datatype must be matched by a 1-bit wide UIntType.
    • The mask must be a reference, subfield, or subindex The bitmask is a series of concatenations of the single mask bit over the length of the corresponding ground type, e.g.:
    wire mask: {x: UInt<1>, y: UInt<1>}
    wire data: {x: UInt<2>, y: SInt<2>}
    // this would return:
    cat(cat(mask.x, mask.x), cat(mask.y, mask.y))
  41. package wiring

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Ungrouped