Object

firrtl.passes.memlib

RenameAnnotatedMemoryPorts

Related Doc: package memlib

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object RenameAnnotatedMemoryPorts extends Transform with Pass

Changes memory port names to standard port names (i.e. RW0 instead T_408)

Linear Supertypes
Pass, Transform, LazyLogging, AnyRef, Any
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  1. RenameAnnotatedMemoryPorts
  2. Pass
  3. Transform
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Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any
  5. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  6. def createMemProto(m: DefAnnotatedMemory): DefAnnotatedMemory

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    Renames memory ports to a standard naming scheme:

    Renames memory ports to a standard naming scheme:

    • R0, R1, ... for each read port
    • W0, W1, ... for each write port
    • RW0, RW1, ... for each readwrite port
  7. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  8. def equals(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  9. def execute(state: CircuitState): CircuitState

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    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes
    PassTransform
  10. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  11. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any
  12. def getMemPortMap(m: DefAnnotatedMemory, memPortMap: MemPortMap): Unit

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    Maps the serialized form of all memory port field names to the corresponding new memory port field Expression.

    Maps the serialized form of all memory port field names to the corresponding new memory port field Expression. E.g.:

    • ("m.read.addr") becomes (m.R0.addr)
  13. final def getMyAnnotations(state: CircuitState): Seq[Annotation]

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    Convenience method to get annotations relevant to this Transform

    Convenience method to get annotations relevant to this Transform

    state

    The CircuitState form which to extract annotations

    returns

    A collection of annotations

    Definition Classes
    Transform
  14. def hashCode(): Int

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    Definition Classes
    AnyRef → Any
  15. def inputForm: CircuitForm

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    The firrtl.CircuitForm that this transform requires to operate on

    The firrtl.CircuitForm that this transform requires to operate on

    Definition Classes
    PassTransform
  16. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any
  17. val logger: Logger

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    Definition Classes
    LazyLogging
  18. def name: String

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    A convenience function useful for debugging and error messages

    A convenience function useful for debugging and error messages

    Definition Classes
    Transform
  19. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  20. final def notify(): Unit

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    Definition Classes
    AnyRef
  21. final def notifyAll(): Unit

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    Definition Classes
    AnyRef
  22. def outputForm: CircuitForm

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    The firrtl.CircuitForm that this transform outputs

    The firrtl.CircuitForm that this transform outputs

    Definition Classes
    PassTransform
  23. def run(c: Circuit): Circuit

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    Definition Classes
    RenameAnnotatedMemoryPortsPass
  24. final def runTransform(state: CircuitState): CircuitState

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    Perform the transform and update annotations.

    Perform the transform and update annotations.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes
    Transform
  25. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef
  26. def toString(): String

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    Definition Classes
    AnyRef → Any
  27. def updateMemMods(m: DefModule): DefModule

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    Replaces candidate memories and their references with standard port names

  28. def updateMemStmts(memPortMap: MemPortMap)(s: Statement): Statement

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    Replaces candidate memories with memories with standard port names Does not update the references (this is done via updateStmtRefs)

  29. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  30. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  31. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from Pass

Inherited from Transform

Inherited from LazyLogging

Inherited from AnyRef

Inherited from Any

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