Package

firrtl

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package firrtl

Visibility
  1. Public
  2. All

Type Members

  1. case class AnnotationMap(annotations: Seq[Annotation]) extends Product with Serializable

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    Container of all annotations for a Firrtl compiler.

  2. case class CDefMPort(info: Info, name: String, tpe: Type, mem: String, exps: Seq[Expression], direction: MPortDir) extends Statement with Product with Serializable

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  3. case class CDefMemory(info: Info, name: String, tpe: Type, size: Int, seq: Boolean) extends Statement with Product with Serializable

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  4. class ChirrtlToHighFirrtl extends CoreTransform

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    This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".

    This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting circuit has only IR nodes, not WIR.

  5. sealed abstract class CircuitForm extends Ordered[CircuitForm]

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    Current form of the Firrtl Circuit

    Current form of the Firrtl Circuit

    Form is a measure of addition restrictions on the legality of a Firrtl circuit. There is a notion of "highness" and "lowness" implemented in the compiler by extending scala.math.Ordered. "Lower" forms add additional restrictions compared to "higher" forms. This means that "higher" forms are strictly supersets of the "lower" forms. Thus, that any transform that operates on HighForm can also operate on MidForm or LowForm

  6. case class CircuitState(circuit: Circuit, form: CircuitForm, annotations: Option[AnnotationMap] = None, renames: Option[RenameMap] = None) extends Product with Serializable

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    Current State of the Circuit

    Current State of the Circuit

    circuit

    The current state of the Firrtl AST

    form

    The current form of the circuit

    annotations

    The current collection of Annotation

    renames

    A map of Named things that have been renamed. Generally only a return value from Transforms

  7. case class CommonOptions(topName: String = "", targetDirName: String = ".", globalLogLevel: logger.LogLevel.Value = LogLevel.None, logToFile: Boolean = false, logClassNames: Boolean = false, classLogLevels: Map[String, logger.LogLevel.Value] = Map.empty, programArgs: Seq[String] = Seq.empty) extends ComposableOptions with Product with Serializable

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    Most of the chisel toolchain components require a topName which defines a circuit or a device under test.

    Most of the chisel toolchain components require a topName which defines a circuit or a device under test. Much of the work that is done takes place in a directory. It would be simplest to require topName to be defined but in practice it is preferred to defer this. For example, in chisel, by deferring this it is possible for the execute there to first elaborate the circuit and then set the topName from that if it has not already been set.

  8. trait Compiler extends LazyLogging

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  9. trait ComposableOptions extends AnyRef

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    Use this trait to define an options class that can add its private command line options to a externally declared parser

  10. trait Constraint extends AnyRef

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  11. sealed abstract class CoreTransform extends SeqTransform

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  12. sealed abstract class EmitAnnotation extends AnyRef

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  13. sealed abstract class EmittedAnnotation[T <: EmittedComponent] extends AnyRef

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    Super class for Annotations containing emitted components

    Super class for Annotations containing emitted components

    Note

    These annotations cannot be serialized and deserialized to/from an annotation file

  14. sealed abstract class EmittedCircuit extends EmittedComponent

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  15. sealed abstract class EmittedComponent extends AnyRef

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  16. final case class EmittedFirrtlCircuit(name: String, value: String) extends EmittedCircuit with Product with Serializable

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  17. final case class EmittedFirrtlModule(name: String, value: String) extends EmittedModule with Product with Serializable

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  18. sealed abstract class EmittedModule extends EmittedComponent

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  19. final case class EmittedVerilogCircuit(name: String, value: String) extends EmittedCircuit with Product with Serializable

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  20. final case class EmittedVerilogModule(name: String, value: String) extends EmittedModule with Product with Serializable

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  21. trait Emitter extends Transform

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    Defines old API for Emission.

    Defines old API for Emission. Deprecated

  22. case class EmitterException(message: String) extends PassException with Product with Serializable

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  23. class ExecutionOptionsManager extends HasParser with HasCommonOptions

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  24. case class ExpWidth(arg1: Width) extends Width with HasMapWidth with Product with Serializable

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  25. class FIRRTLException extends Exception

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  26. sealed abstract class FirrtlEmitter extends Transform with Emitter

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  27. case class FirrtlExecutionFailure(message: String) extends FirrtlExecutionResult with Product with Serializable

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    The firrtl compilation failed.

    The firrtl compilation failed.

    message

    Some kind of hint as to what went wrong.

  28. case class FirrtlExecutionOptions(inputFileNameOverride: String = "", outputFileNameOverride: String = "", compilerName: String = "verilog", infoModeName: String = "append", inferRW: Seq[String] = Seq.empty, firrtlSource: Option[String] = None, customTransforms: Seq[Transform] = List.empty, annotations: List[Annotation] = List.empty, annotationFileNameOverride: String = "", outputAnnotationFileName: String = "", forceAppendAnnoFile: Boolean = false, emitOneFilePerModule: Boolean = false, dontCheckCombLoops: Boolean = false, noDCE: Boolean = false) extends ComposableOptions with Product with Serializable

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    The options that firrtl supports in callable component sense

    The options that firrtl supports in callable component sense

    inputFileNameOverride

    default is targetDir/topName.fir

    outputFileNameOverride

    default is targetDir/topName.v the .v is based on the compilerName parameter

    compilerName

    which compiler to use

    annotations

    annotations to pass to compiler

  29. sealed trait FirrtlExecutionResult extends AnyRef

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  30. case class FirrtlExecutionSuccess(emitType: String, emitted: String) extends FirrtlExecutionResult with Product with Serializable

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    Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile

    Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile

    emitType

    The name of the compiler used, currently "high", "middle", "low", "verilog", or "sverilog"

    emitted

    The emitted result of compilation

  31. trait Gender extends AnyRef

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  32. trait HasCommonOptions extends AnyRef

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  33. trait HasFirrtlOptions extends AnyRef

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  34. abstract class HasParser extends AnyRef

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  35. class HighFirrtlCompiler extends Compiler

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    Emits input circuit Will replace Chirrtl constructs with Firrtl

  36. class HighFirrtlEmitter extends FirrtlEmitter

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  37. class HighFirrtlToMiddleFirrtl extends CoreTransform

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    Expands aggregate connects, removes dynamic accesses, and when statements.

    Expands aggregate connects, removes dynamic accesses, and when statements. Checks for uninitialized values. Must accept a well-formed graph. Operates on working IR nodes.

  38. class IRToWorkingIR extends CoreTransform

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    Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)

  39. case class InvalidEscapeCharException(message: String) extends ParserException with Product with Serializable

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  40. case class InvalidStringLitException(message: String) extends ParserException with Product with Serializable

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  41. trait Kind extends AnyRef

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  42. abstract class LexerHelper extends AnyRef

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  43. class LowFirrtlCompiler extends Compiler

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    Emits lowered input circuit

  44. class LowFirrtlEmitter extends FirrtlEmitter

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  45. class LowFirrtlOptimization extends CoreTransform

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    Runs a series of optimization passes on LowFirrtl

    Runs a series of optimization passes on LowFirrtl

    Note

    This is currently required for correct Verilog emission TODO Fix the above note

  46. abstract class MPortDir extends FirrtlNode

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  47. case class MaxWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable

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  48. class MemoizedHash[T] extends AnyRef

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  49. class MiddleFirrtlCompiler extends Compiler

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    Emits middle Firrtl input circuit

  50. class MiddleFirrtlEmitter extends FirrtlEmitter

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  51. class MiddleFirrtlToLowFirrtl extends CoreTransform

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    Expands all aggregate types into many ground-typed components.

    Expands all aggregate types into many ground-typed components. Must accept a well-formed graph of only middle Firrtl features. Operates on working IR nodes.

  52. case class MinWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable

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  53. case class MinusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable

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  54. class ModuleGraph extends AnyRef

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    Maintains a one to many graph of each modules instantiated child module.

    Maintains a one to many graph of each modules instantiated child module. This graph can be searched for a path from a child module back to one of it's parents. If one is found a recursive loop has happened The graph is a map between the name of a node to set of names of that nodes children

  55. class Namespace extends AnyRef

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  56. final case class OneFilePerModule(targetDir: String) extends OutputConfig with Product with Serializable

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  57. sealed abstract class OutputConfig extends AnyRef

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    Firrtl output configuration specified by FirrtlExecutionOptions

    Firrtl output configuration specified by FirrtlExecutionOptions

    Derived from the fields of the execution options

    See also

    FirrtlExecutionOptions.getOutputConfig

  58. case class ParameterNotSpecifiedException(message: String) extends ParserException with Product with Serializable

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  59. case class ParameterRedefinedException(message: String) extends ParserException with Product with Serializable

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  60. class ParserException extends Exception

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  61. case class PlusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable

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  62. final class RenameMap extends AnyRef

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    Map old names to new names

    Map old names to new names

    Transforms that modify names should return a RenameMap with the CircuitState These are mutable datastructures for convenience

  63. class ResolveAndCheck extends CoreTransform

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    Resolves types, kinds, and genders, and checks the circuit legality.

    Resolves types, kinds, and genders, and checks the circuit legality. Operates on working IR nodes and high Firrtl.

  64. abstract class SeqTransform extends Transform with SeqTransformBased

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    For transformations that are simply a sequence of transforms

  65. trait SeqTransformBased extends AnyRef

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  66. final case class SingleFile(targetFile: String) extends OutputConfig with Product with Serializable

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  67. abstract class Transform extends LazyLogging

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    The basic unit of operating on a Firrtl AST

  68. case class VRandom(width: BigInt) extends Expression with Product with Serializable

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  69. case class VarWidth(name: String) extends Width with HasMapWidth with Product with Serializable

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  70. class VerilogCompiler extends Compiler

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    Emits Verilog

  71. class VerilogEmitter extends SeqTransform with Emitter

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  72. class Visitor extends FIRRTLBaseVisitor[FirrtlNode]

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  73. case class WDefInstance(info: Info, name: String, module: String, tpe: Type) extends Statement with IsDeclaration with Product with Serializable

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  74. case class WDefInstanceConnector(info: Info, name: String, module: String, tpe: Type, portCons: Seq[(Expression, Expression)]) extends Statement with IsDeclaration with Product with Serializable

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  75. class WGeq extends Constraint

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  76. case class WRef(name: String, tpe: Type, kind: Kind, gender: Gender) extends Expression with Product with Serializable

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  77. case class WSubAccess(expr: Expression, index: Expression, tpe: Type, gender: Gender) extends Expression with Product with Serializable

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  78. case class WSubField(expr: Expression, name: String, tpe: Type, gender: Gender) extends Expression with Product with Serializable

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  79. case class WSubIndex(expr: Expression, value: Int, tpe: Type, gender: Gender) extends Expression with Product with Serializable

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  80. class WrappedExpression extends AnyRef

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  81. class WrappedType extends AnyRef

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  82. class WrappedWidth extends AnyRef

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Value Members

  1. object Addw extends PrimOp with Product with Serializable

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  2. object BIGENDER extends Gender with Product with Serializable

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  3. object ChirrtlForm extends CircuitForm with Product with Serializable

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    Chirrtl Form

    Chirrtl Form

    The form of the circuit emitted by Chisel. Not a true Firrtl form. Includes cmem, smem, and mport IR nodes which enable declaring memories separately form their ports. A "Higher" form than HighForm

    See CDefMemory and CDefMPort

  4. object CompilerUtils extends LazyLogging

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  5. object Driver

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    The driver provides methods to access the firrtl compiler.

    The driver provides methods to access the firrtl compiler. Invoke the compiler with either a FirrtlExecutionOption

    Examples:
    1. firrtl.Driver.execute(Array("--top-name Dummy --compiler verilog".split(" +"))

      each approach has its own endearing aspects

    2. ,
    3. val optionsManager = new ExecutionOptionsManager("firrtl")
      optionsManager.register(
          FirrtlExecutionOptionsKey ->
          new FirrtlExecutionOptions(topName = "Dummy", compilerName = "verilog"))
      firrtl.Driver.execute(optionsManager)

      or a series of command line arguments

    See also

    CompilerUtils.mergeTransforms to see how customTransformations are inserted

    firrtlTests/DriverSpec.scala in the test directory for a lot more examples

  6. object Dshlw extends PrimOp with Product with Serializable

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  7. object EmitAllModulesAnnotation extends EmitAnnotation

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  8. object EmitCircuitAnnotation extends EmitAnnotation

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  9. object EmittedCircuitAnnotation

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  10. object EmittedFirrtlCircuitAnnotation extends EmittedAnnotation[EmittedFirrtlCircuit]

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  11. object EmittedFirrtlModuleAnnotation extends EmittedAnnotation[EmittedFirrtlModule]

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  12. object EmittedModuleAnnotation

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  13. object EmittedVerilogCircuitAnnotation extends EmittedAnnotation[EmittedVerilogCircuit]

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  14. object EmittedVerilogModuleAnnotation extends EmittedAnnotation[EmittedVerilogModule]

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  15. object EmptyExpression extends Expression with Product with Serializable

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  16. object ExpKind extends Kind with Product with Serializable

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  17. object FEMALE extends Gender with Product with Serializable

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  18. object FileUtils

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  19. object HighForm extends CircuitForm with Product with Serializable

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    High Form

    High Form

    As detailed in the Firrtl specification https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf

    Also see firrtl.ir

  20. object InstanceKind extends Kind with Product with Serializable

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  21. object LowForm extends CircuitForm with Product with Serializable

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    Low Form

    Low Form

    The "lowest" form. In addition to the restrictions in MidForm:

    • All aggregate types (vector/bundle) must have been removed
    • All implicit truncations must be made explicit
  22. object MALE extends Gender with Product with Serializable

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  23. object MInfer extends MPortDir with Product with Serializable

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  24. object MRead extends MPortDir with Product with Serializable

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  25. object MReadWrite extends MPortDir with Product with Serializable

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  26. object MWrite extends MPortDir with Product with Serializable

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  27. object Mappers

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  28. object MemKind extends Kind with Product with Serializable

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  29. object MemoizedHash

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  30. object MidForm extends CircuitForm with Product with Serializable

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    Middle Form

    Middle Form

    A "lower" form than HighForm with the following restrictions:

    • All widths must be explicit
    • All whens must be removed
    • There can only be a single connection to any element
  31. object Namespace

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  32. object NodeKind extends Kind with Product with Serializable

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  33. object Parser extends LazyLogging

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  34. object PoisonKind extends Kind with Product with Serializable

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  35. object PortKind extends Kind with Product with Serializable

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  36. object PrimOps extends LazyLogging

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    Definitions and Utility functions for ir.PrimOps

  37. object RegKind extends Kind with Product with Serializable

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  38. object RenameMap

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  39. object Shlw extends PrimOp with Product with Serializable

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  40. object Subw extends PrimOp with Product with Serializable

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  41. object TargetDirAnnotation extends GlobalCircuitAnnotation

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    annotations.GlobalCircuitAnnotation that contains the CommonOptions target directory

  42. object UNKNOWNGENDER extends Gender with Product with Serializable

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  43. object UnknownForm extends CircuitForm with Product with Serializable

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    Unknown Form

    Unknown Form

    Often passes may modify a circuit (e.g. InferTypes), but return a circuit in the same form it was given.

    For this use case, use UnknownForm. It cannot be compared against other forms.

    TODO(azidar): Replace with PreviousForm, which more explicitly encodes this requirement.

  44. object Utils extends LazyLogging

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  45. object WDefInstance extends Serializable

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  46. object WGeq

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  47. object WInvalid extends Expression with Product with Serializable

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  48. object WRef extends Serializable

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  49. object WSubField extends Serializable

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  50. object WVoid extends Expression with Product with Serializable

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  51. object WireKind extends Kind with Product with Serializable

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  52. object WrappedExpression

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  53. object WrappedType

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  54. object WrappedWidth

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  55. package altIR

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  56. package analyses

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  57. package annotations

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  58. package antlr

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  59. object bitWidth

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  60. object castRhs

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  61. object connectFields

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  62. object flattenType

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  63. object fromBits

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  64. object getWidth

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  65. package graph

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  66. package ir

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  67. package passes

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  68. object seqCat

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  69. object toBits

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    Given an expression, return an expression consisting of all sub-expressions concatenated (or flattened).

  70. package transforms

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  71. package util

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