Container of all annotations for a Firrtl compiler.
This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".
Current form of the Firrtl Circuit
Current State of the Circuit
Most of the chisel toolchain components require a topName which defines a circuit or a device under test.
Use this trait to define an options class that can add its private command line options to a externally declared parser
Super class for Annotations containing emitted components
These annotations cannot be serialized and deserialized to/from an annotation file
Defines old API for Emission.
The firrtl compilation failed.
Some kind of hint as to what went wrong.
The options that firrtl supports in callable component sense
default is targetDir/topName.fir
default is targetDir/topName.v the .v is based on the compilerName parameter
which compiler to use
annotations to pass to compiler
Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile
The name of the compiler used, currently "high", "middle", "low", "verilog", or "sverilog"
The emitted result of compilation
Emits input circuit Will replace Chirrtl constructs with Firrtl
Expands aggregate connects, removes dynamic accesses, and when statements.
Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)
Emits lowered input circuit
Runs a series of optimization passes on LowFirrtl
This is currently required for correct Verilog emission TODO Fix the above note
Emits middle Firrtl input circuit
Expands all aggregate types into many ground-typed components.
Maintains a one to many graph of each modules instantiated child module.
Firrtl output configuration specified by FirrtlExecutionOptions
Map old names to new names
Resolves types, kinds, and genders, and checks the circuit legality.
For transformations that are simply a sequence of transforms
The basic unit of operating on a Firrtl AST
The driver provides methods to access the firrtl compiler.
firrtl.Driver.execute(Array("--top-name Dummy --compiler verilog".split(" +"))
each approach has its own endearing aspects
val optionsManager = new ExecutionOptionsManager("firrtl") optionsManager.register( FirrtlExecutionOptionsKey -> new FirrtlExecutionOptions(topName = "Dummy", compilerName = "verilog")) firrtl.Driver.execute(optionsManager)
or a series of command line arguments
CompilerUtils.mergeTransforms to see how customTransformations are inserted
firrtlTests/DriverSpec.scala in the test directory for a lot more examples
Definitions and Utility functions for ir.PrimOps
Given an expression, return an expression consisting of all sub-expressions concatenated (or flattened).