object dontTouch
Marks that a signal should not be removed by Chisel and Firrtl optimization passes
- Source
- dontTouch.scala
class MyModule extends Module { val io = IO(new Bundle { val a = Input(UInt(32.W)) val b = Output(UInt(32.W)) }) io.b := io.a val dead = io.a +% 1.U // normally dead would be pruned by DCE dontTouch(dead) // Marking it as such will preserve it }
- Note
Calling this on Data creates an annotation that Chisel emits to a separate annotations file. This file must be passed to FIRRTL independently of the
.fir
file. The execute methods in chisel3.Driver will pass the annotations to FIRRTL automatically.
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def
apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T
Marks a signal to be preserved in Chisel and Firrtl
Marks a signal to be preserved in Chisel and Firrtl
- data
The signal to be marked
- returns
Unmodified signal
data
- Note
Requires the argument to be bound to hardware
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.