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chisel3

experimental

package experimental

Package for experimental features, which may have their API changed, be removed, etc.

Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

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package.scala
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Type Members

  1. final class Analog extends Element

    Data type for representing bidirectional bitvectors of a given width

    Data type for representing bidirectional bitvectors of a given width

    Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

    Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

    Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

    Note

    This API is experimental and subject to change

  2. abstract class BaseModule extends HasId with IsInstantiable

    Abstract base class for Modules, an instantiable organizational unit for RTL.

  3. class BundleLiteralException extends ChiselException
  4. trait ChiselAnnotation extends AnyRef

    Interface for Annotations in Chisel

    Interface for Annotations in Chisel

    Defines a conversion to a corresponding FIRRTL Annotation

  5. type ChiselEnum = EnumFactory
  6. implicit final class ChiselRange extends AnyVal
  7. type ClonePorts = internal.BaseModule.ClonePorts

    A record containing the results of CloneModuleAsRecord The apply method is retrieves the element with the supplied name.

  8. type Direction = ActualDirection
  9. case class DoubleParam(value: Double) extends Param with Product with Serializable
  10. abstract class EnumFactory extends AnyRef
  11. abstract class EnumType extends Element
  12. abstract class ExtModule extends BaseBlackBox

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.

    Annotations
    @nowarn()
    Example:
    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

      IBUFDS #(.DIFF_TERM("TRUE"),
               .IOSTANDARD("DEFAULT")) ibufds (
       .IB(ibufds_IB),
       .I(ibufds_I),
       .O(ibufds_O)
      );

      To instantiate it, a BlackBox can be used like following:

      import chisel3._
      import chisel3.experimental._
      
      // Example with Xilinx differential buffer IBUFDS
      class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                         "IOSTANDARD" -> "DEFAULT"
                           )) {
        val O = IO(Output(Clock()))
        val I = IO(Input(Clock()))
        val IB = IO(Input(Clock()))
      }
    Note

    The parameters API is experimental and may change

  13. sealed class FixedPoint extends Bits with Num[FixedPoint] with HasBinaryPoint

    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    IMPORTANT: The API provided here is experimental and may change in the future.

  14. final class HWTuple10[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data, +I <: Data, +J <: Data] extends Bundle

    Data equivalent of Scala's Tuple9

    Data equivalent of Scala's Tuple9

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

  15. final class HWTuple2[+A <: Data, +B <: Data] extends Bundle

    Data equivalent of Scala's Tuple2

    Data equivalent of Scala's Tuple2

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple2 in chisel3.experimental.conversions

  16. final class HWTuple3[+A <: Data, +B <: Data, +C <: Data] extends Bundle

    Data equivalent of Scala's Tuple3

    Data equivalent of Scala's Tuple3

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple3 in chisel3.experimental.conversions

  17. final class HWTuple4[+A <: Data, +B <: Data, +C <: Data, +D <: Data] extends Bundle

    Data equivalent of Scala's Tuple4

    Data equivalent of Scala's Tuple4

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple4 in chisel3.experimental.conversions

  18. final class HWTuple5[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data] extends Bundle

    Data equivalent of Scala's Tuple5

    Data equivalent of Scala's Tuple5

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple5 in chisel3.experimental.conversions

  19. final class HWTuple6[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data] extends Bundle

    Data equivalent of Scala's Tuple6

    Data equivalent of Scala's Tuple6

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple6 in chisel3.experimental.conversions

  20. final class HWTuple7[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data] extends Bundle

    Data equivalent of Scala's Tuple7

    Data equivalent of Scala's Tuple7

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple7 in chisel3.experimental.conversions

  21. final class HWTuple8[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data] extends Bundle

    Data equivalent of Scala's Tuple8

    Data equivalent of Scala's Tuple8

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple8 in chisel3.experimental.conversions

  22. final class HWTuple9[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data, +I <: Data] extends Bundle

    Data equivalent of Scala's Tuple9

    Data equivalent of Scala's Tuple9

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

  23. trait HasBinaryPoint extends AnyRef

    Chisel types that have binary points support retrieving literal values as Double or BigDecimal

  24. case class IntParam(value: BigInt) extends Param with Product with Serializable
  25. sealed class Interval extends Bits with Num[Interval] with HasBinaryPoint

    A sealed class representing a fixed point number that has a range, an additional parameter that can determine a minimum and maximum supported value.

    A sealed class representing a fixed point number that has a range, an additional parameter that can determine a minimum and maximum supported value. The range can be used to reduce the required widths particularly in primitive operations with other Intervals, the canonical example being

    val one = 1.I
    val six = Seq.fill(6)(one).reduce(_ + _)

    A UInt computed in this way would require a Width binary point The width and binary point may be inferred.

    IMPORTANT: The API provided here is experimental and may change in the future.

  26. trait NoChiselNamePrefix extends AnyRef

    Do not name instances of this type in chiselName

    Do not name instances of this type in chiselName

    By default, chiselName will include val names of instances of annotated classes as a prefix in final naming. Mixing in this trait to a class, object, or anonymous class instances will exclude the val name from chiselName naming.

    Example:
    1. import chisel3._
      import chisel3.experimental.{chiselName, NoChiselNamePrefix}
      
      // Note that this is not a Module
      @chiselName
      class Counter(w: Int) {
        val myReg = RegInit(0.U(w.W))
        myReg := myReg + 1.U
      }
      
      @chiselName
      class MyModule extends Module {
        val io = IO(new Bundle {
          val out = Output(UInt(8.W))
        })
        // Name of myReg will be "counter0_myReg"
        val counter0 = new Counter(8)
        // Name of myReg will be "myReg"
        val counter1 = new Counter(8) with NoChiselNamePrefix
        io.out := counter0.myReg + counter1.myReg
      }
  27. sealed abstract class Param extends AnyRef

    Parameters for BlackBoxes

  28. sealed trait PrivateType extends AnyRef

    Use PrivateObject to force users to specify width and binaryPoint by name

  29. case class RawParam(value: String) extends Param with Product with Serializable

    Unquoted String

  30. trait RunFirrtlTransform extends ChiselAnnotation

    Mixin for ChiselAnnotation that instantiates an associated FIRRTL Transform when this Annotation is present during a run of Driver.execute.

    Mixin for ChiselAnnotation that instantiates an associated FIRRTL Transform when this Annotation is present during a run of Driver.execute. Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking FIRRTL.

  31. case class StringParam(value: String) extends Param with Product with Serializable
  32. class VecLiteralException extends ChiselException
  33. macro class chiselName extends internal.naming.chiselName

    Experimental macro for naming Chisel hardware values

    Experimental macro for naming Chisel hardware values

    By default, Chisel uses reflection for naming which only works for public fields of Bundle and Module classes. Applying this macro annotation to a class or object enables Chisel to name any hardware values within the annotated class or object.

    Annotations
    @compileTimeOnly( ... )
    Example:
    1. import chisel3._
      import chisel3.experimental.chiselName
      
      @chiselName
      class MyModule extends Module {
        val io = IO(new Bundle {
          val in = Input(UInt(8.W))
          val out = Output(UInt(8.W))
        })
        def createReg(): Unit = {
          // @chiselName allows Chisel to name this Reg
          val myReg = RegInit(io.in)
          io.out := myReg
        }
        createReg()
      }
  34. macro class dump extends internal.naming.dump
    Annotations
    @compileTimeOnly( ... )
  35. macro class treedump extends internal.naming.treedump
    Annotations
    @compileTimeOnly( ... )

Value Members

  1. val Direction: ActualDirection.type
  2. def FlatIO[T <: Record](gen: ⇒ T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T

    The same as IO except there is no prefix for the name of the val

  3. implicit def fromBigIntToIntParam(x: BigInt): IntParam
  4. implicit def fromDoubleToDoubleParam(x: Double): DoubleParam
  5. implicit def fromIntToIntParam(x: Int): IntParam
  6. implicit def fromLongToIntParam(x: Long): IntParam
  7. implicit def fromStringToStringParam(x: String): StringParam
  8. val noPrefix: internal.noPrefix.type
  9. val prefix: internal.prefix.type
  10. val requireIsChiselType: internal.requireIsChiselType.type
  11. val requireIsHardware: internal.requireIsHardware.type
  12. object Analog

    Object that provides factory methods for Analog objects

    Object that provides factory methods for Analog objects

    Note

    This API is experimental and subject to change

  13. object BaseModule
  14. object BundleLiterals
  15. object CloneModuleAsRecord
  16. object DataMirror

    Experimental hardware construction reflection API

  17. object EnumAnnotations
  18. object FixedPoint extends NumObject

    Factory and convenience methods for the FixedPoint class IMPORTANT: The API provided here is experimental and may change in the future.

  19. object IO
  20. object Interval extends NumObject

    Factory and convenience methods for the Interval class IMPORTANT: The API provided here is experimental and may change in the future.

  21. object Trace

    The util that records the reference map from original Data/Module annotated in Chisel and final FIRRTL.

    The util that records the reference map from original Data/Module annotated in Chisel and final FIRRTL.

    Example:
    1. class Dut extends Module {
        val a = WireDefault(Bool())
        Trace.traceName(a)
      }
      val annos = (new ChiselStage).execute(Seq(ChiselGeneratorAnnotation(() => new Dut)))
      val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[CollideModule]
      // get final reference of `a` Seq(ReferenceTarget("Dut", "Dut", Seq.empty, "a", Seq.empty))
      val firrtlReferenceOfDutA = finalTarget(annos)(dut.a)
  22. object VecLiterals

    This class provides the Lit method needed to define a Vec literal

  23. object annotate
  24. object attach
  25. object doNotDedup

    Marks that a module to be ignored in Dedup Transform in Firrtl pass

    Marks that a module to be ignored in Dedup Transform in Firrtl pass

    Example:
    1.  def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
         val m = Module(new Module {
           val io = IO(new Bundle {
             val a = Input(UInt(32.W))
             val b = Input(UInt(32.W))
             val out = Output(UInt(32.W))
           })
           override def desiredName = "adder_" + myNname
           io.out := io.a + io.b
         })
         doNotDedup(m)
         m.io.a := a
         m.io.b := b
         m.io.out
       }
      
      class AdderTester extends Module
       with ConstantPropagationTest {
       val io = IO(new Bundle {
         val a = Input(UInt(32.W))
         val b = Input(UInt(32.W))
         val out = Output(Vec(2, UInt(32.W)))
       })
      
       io.out(0) := fullAdder(io.a, io.b, "mod1")
       io.out(1) := fullAdder(io.a, io.b, "mod2")
      }
    Note

    Calling this on Data creates an annotation that Chisel emits to a separate annotations file. This file must be passed to FIRRTL independently of the .fir file. The execute methods in chisel3.Driver will pass the annotations to FIRRTL automatically.

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