Packages

object doNotDedup

Marks that a module to be ignored in Dedup Transform in Firrtl pass

Source
Annotation.scala
Example: 

  1.  def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
   val m = Module(new Module {
     val io = IO(new Bundle {
       val a = Input(UInt(32.W))
       val b = Input(UInt(32.W))
       val out = Output(UInt(32.W))
     })
     override def desiredName = "adder_" + myNname
     io.out := io.a + io.b
   })
   doNotDedup(m)
   m.io.a := a
   m.io.b := b
   m.io.out
 }

class AdderTester extends Module
 with ConstantPropagationTest {
 val io = IO(new Bundle {
   val a = Input(UInt(32.W))
   val b = Input(UInt(32.W))
   val out = Output(Vec(2, UInt(32.W)))
 })

 io.out(0) := fullAdder(io.a, io.b, "mod1")
 io.out(1) := fullAdder(io.a, io.b, "mod2")
}
Note

Calling this on Data creates an annotation that Chisel emits to a separate annotations file. This file must be passed to FIRRTL independently of the .fir file. The execute methods in chisel3.Driver will pass the annotations to FIRRTL automatically.

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  1. final def !=(arg0: Any): Boolean
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  2. final def ##(): Int
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  3. final def ==(arg0: Any): Boolean
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  4. def apply[T <: RawModule](module: T)(implicit compileOptions: CompileOptions): Unit

    Marks a module to be ignored in Dedup Transform in Firrtl

    Marks a module to be ignored in Dedup Transform in Firrtl

    module

    The module to be marked

    returns

    Unmodified signal module

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