trait BackendCompilationUtilities extends LazyLogging
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- @deprecated
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(Since version Chisel 3.5) Use object firrtl.util.BackendCompilationUtilities instead
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- Driver.scala
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def
compileFirrtlToVerilog(prefix: String, dir: File): Boolean
Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
- prefix
basename of the file
- dir
directory where file lives
- returns
true if compiler completed successfully
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- @deprecated
- Deprecated
(Since version Chisel 3.5) Use ChiselStage instead
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.