• Chisel/FIRRTL
  • Chisel3
  • Resources
    • FAQ
  • Cookbooks
    • General Cookbook
    • Naming Cookbook
    • Troubleshooting
    • DataView Cookbook
    • Hierarchy Cookbook
  • Explanations
    • Motivation
    • Supported Hardware
    • Connectable
    • Data Types
    • Dataview
    • Bundles and Vecs
    • Combinational Circuits
    • Operators
    • Width Inference
    • Functional Abstraction
    • Ports
    • Modules
    • Sequential Circuits
    • Memories
    • Interfaces and Connections
    • Blackboxes
    • Intrinsics
    • Enumerations
    • Functional Module Creation
    • Muxes and Input Selection
    • Multiple Clock Domains
    • Reset
    • Polymorphism and Parameterization
    • Printing in Chisel
    • Naming
    • Unconnected Wires
    • Intrinsic Modules
    • Annotations
    • Deep Dive into Connection Operators
    • Chisel Type vs Scala Type
    • Decoders
    • Source Locators
  • Appendix
    • Chisel3 vs. Chisel2
    • Experimental Features
    • Versioning
    • Upgrading From Chisel 3.4 to 3.5
    • Upgrading From Scala 2.11
  • Developers
    • Style Guide
    • sbt Subproject
    • Test Coverage
  • API Documentation
    • Latest
    • 6.0
    • 5.0
    • 3.6
    • 3.5

    Appendix

    This section covers some less-common Chisel topics.

    • Differences between Chisel3 and Chisel2
    • Experimental Features
    • Upgrading from Scala 2.11
    • Upgrading from Chisel 3.4
    • Versioning